Zhenghong-Jiang

ZHENGHONG JIANG (江政泓)

Postdoc Associate [CV]
Computer Systems Laboratory
School of Electrical and Computer Engineering
Cornell University

Office: 471E Rhodes Hall, Ithaca, NY 14850
Email: jz763-at-cornell.edu
Phone: (607)262-4091


I am a Postdoctoral Research Associate under the supervision of Prof. Zhiru Zhang in the Computer Systems Laboratory (CSL) at Cornell University. My research interests are High-Level Synthesis and Hardware Security.
I received my Ph.D. degree in Microelectronics and Solid State Electronics from Institute of Electronics, Chinese Academy of Sciences (Beijing, China) in 2016. I have a B.S. in Electronic Science and Technology from Huazhong University of Science and Technology.


Research Interest

  • High-Level Synthesis
  • Hardware Security with Information-Flow Enforcement
  • Logic Synthesis and Technology Mapping on FPGA

Publications

[C6] Z. Jiang, H. Jin, G. E. Suh, and Z. Zhang, Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. Design Automation Conference (DAC), 2019.
[C5] Z. Jiang, S. Dai, G. E. Suh, and Z. Zhang, High-Level Synthesis with Timing-Sensitive Information Flow Enforcement. Int'l Conf. on Computer Aided Design (ICCAD), 2018.
[C4] Z. Huang, X. Wei, G. Zgheib, W. Li, Y. Lin, Z. Jiang, K. Tu, P. Ienne, and H. Yang. NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. Int'l Symp. on Field-Programmable Gate Arrays (FPGA), 2017.
[C3] Y. Lin, Z. Jiang, C. Fu, H. K.H. So, and H. Yang. FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. Int'l Symp. on Highly-Efficient Accelerator and Reconfigurable Technologies (HEART), 2017.
[C2] Z. Jiang, G. Zgheib, Y. Lin, D. Novo, Z. Huang, L. Yang, H. Yang, and P. Ienne. A Technology Mapper for Depth-Constrained FPGA Logic Cells. Int'l Conf. on Field Programmable Logic and Applications (FPL), 2015.
[C1] Z. Jiang, Y. Lin, L. Yang, F. Wang, and H. Yang. Exploring Architecture Parameters for Dual-Output LUT Based FPGAs. Int'l Conf. on Field Programmable Logic and Applications (FPL), 2014.

[J3] Z. Huang, L. Yang, Z. Jiang, X. Wei, W. Li, Y. Lin, and H. Yang. A Research into Input Crossbar Optimization Method for AIC-based FPGA. Journal of Electronics and Information Technology (Chinese), 2016.
[J2] Z. Huang, H. Yang, L. Yang, W. Li, Z. Jiang and Y. Lin. A Research into Interconnect Architecture of A Novel AIC Based FPGA Cluster. Journal of Electronics and Information Technology (Chinese). vol. 37(12):3030-3040, 2015.
[J1] Z. Jiang, Y. Lin, Z. Huang, L. Yang, and H. Yang. A Mapper for AIC-based FPGAs. Journal of Electronics and Information Technology (Chinese), 2015.


Last update: Feb 18, 2019